1. Field of the Invention
The present invention relates to a semiconductor device including a memory functional body capable of storing an electric charge, and a method of manufacturing the same.
2. Description of the Related Art
A non-volatile memory device comprising a transistor capable of storing two bits of information in one memory cell has been conventionally known. The non-volatile memory device has usually silicon nitride films, each capable of storing an electric charge and thus serving as a memory functional bodies. The silicon nitride films are formed on side surfaces of a gate electrode or on a substrate adjacent to a gate electrode.
A conventional semiconductor device having silicon nitride films, each having an electric charge storing function, is disclosed in, for example, Japanese Unexamined Patent Application Publication No. H09-97849 (document D1). A semiconductor device disclosed in the document D1 will now be described in reference to the accompanying drawings.
FIG. 1 is a cross-sectional side view of a semiconductor device disclosed in the document D1. As shown in FIG. 1, the semiconductor device of the document D1 includes a substrate 115 in which a channel region 111 and first and second main electrode regions 113a, 113b sandwiching the channel region 111 are formed. The first and second main electrode regions 113a and 113b, which are separated from each other, correspond to source and drain regions. In FIG. 1, one of main electrode regions formed at the right side of the channel region 111 corresponds to the first main electrode region 113a. The other of the main electrode regions formed at the left side of the channel region 111 corresponds to the second main electrode region 113b. A gate oxide film 117 is formed on an upper surface of the channel region 111 of the substrate 115. A control gate 119 is formed on the gate oxide film 117. The semiconductor device of the document D1 further includes a silicon nitride film 121 with a uniform thickness. The silicon nitride film 121 covers an upper surface of the control gate 119, both right and left side surfaces of the control gate 119, and an upper surface of the substrate 115 via a lower oxide film 125. The silicon nitride film 121 serves as a memory functional body. The silicon nitride film 121 specifically has a function of accumulating and storing electrons injected thereinto during a writing operation, in other words, an electric charge storing function. Floating gates 123 are respectively formed on upper surface of two portions of the silicon nitride film 121 so as to sandwich the right and left side surfaces of the control gate 119. In FIG. 1, one of the floating gates 123 formed at the right side of the control gate 123 corresponds to a floating gate 123a. The other of the floating gates 123 formed at the left side of the control gate 123 corresponds to a floating gate 123b. The lower silicon oxide 125 with a uniform thickness is formed between the substrate 115 and the silicon nitride film 121. The lower silicon oxide film 125 absorbs a stress difference between the substrate 115 and the silicon nitride film 121. An upper silicon oxide 127 is formed on an upper surface of the silicon nitride film 121. The upper silicon oxide 127 absorbs a stress difference between the silicon nitride film 121 and the floating gates 123. Hereafter, a layered body configured by the lower silicon oxide film 125, the upper silicon oxide film 127, and the silicon nitride film 121 is referenced to as an ONO film 129. In FIG. 1, two portions of the ONO film 129 formed between the floating gates 123 and the substrate 115 respectively correspond to ONO films 129a. Two portions of the ONO film 129 formed between the floating gates 123 and the control gate 119 respectively correspond to ONO films 129b. The ONO film 129 electrically isolates the control gate 119 from the floating gates 123.
In the semiconductor device of the document D1 having such elements and structure, for writing information into the silicon nitride film serving as a memory functional body, a voltage is applied across the control gate 119 and either one of the main electrode regions. The writing operation is performed by injecting electrons into the silicon nitride film 121. The writing operation will now be described in the case that a voltage is applied across the control gate 119 and the first main electrode region 113a. 
In response to an applied voltage across the control gate 119 and the first main electrode region 113a, a voltage is induced on both of the floating gates 123 sandwiching the control gate 119 via the ONO film 129. Since the induced voltage is applied across the floating gate 123b and the second main electrode region 113b located below the floating gate 123b, an electric potential difference between the floating gate 123b and the second main electrode region 113b increases. Under the increased electric potential difference, electrons of the second main electrode region 113b are attracted in a direction toward the floating gate 123b and thus are partially injected into the silicon nitride film 121 located between the floating gate 123b and the second main electrode region 113b. On the other hands, when a voltage is applied across the control gate 119 and the second main electrode region 113b, electrons are injected into the silicon nitride film 121 located between the first floating gate 123a and the first main electrode region 113a. 
In such writing operations, for the purpose of injecting the electrons into the silicon nitride film 121, it is necessary to increase the electric potential difference between one of the floating gates 123 and either one of the first or the second main electrode regions 113 to which the voltage is not applied. It is more preferable that a large induced voltage is applied to the floating gates 123 as much as possible.
The applied voltage on one of the floating gates 123 is dependent upon a coupling ratio Cr between the control gate 119 and one of the floating gates 123. The coupling ratio Cr is given by an equation Cr=C2/(C1+C2). C1 represents an electric capacity of the ONO film 129a formed between the floating gates 123 and the substrate 115. C2 represents an electric capacity an insulating film. In this case, the ONO film 129b formed between the floating gate 123 and the control gate 119 serves as the insulating film. The induced voltage applied to the floating gate 123 is given by a voltage at the control gate 119 multiplied by the coupling ratio Cr. Thus, by increasing the coupling ratio, the induced voltage applied to the floating gate 123 can be increased. As apparent from the equation, it is preferably configured for increasing the coupling ratio that the ONO film 129b formed between the floating gate 123 and the control gate 119 have a large electric capacity value. The electric capacitor of the ONO film 129b can be increased by increasing surface area of the floating gate 123 facing to the control gate 119 via the ONO film 129b. In addition, the electric capacitor of the ONO film 129b formed between the floating gate 123 and the control gate 119 can be increased by decreasing a thickness thereof.
In the semiconductor device disclosed in the document D1, only the side surfaces of the control gate 119 respectively face the floating gates 123 via the insulation film. Thus, the surface area of the control gate 119 facing to the floating gates 123 is relatively small.
In the semiconductor device disclosed in the document D1, the insulation film formed between the floating gate 123 and the control gate 119 corresponds to the ONO film 129 which are configured by the lower silicon oxide film 125, the upper silicon oxide film 127, and the silicon nitride film 121. Since the ONO film 129 includes such the three films, the ONO film 129 is relatively large in thickness.
For these reasons, it is difficult in the semiconductor device of the document D1 to provide a large increase in the electrical potentials at the floating gates 123 and efficiently inject the electrons into the silicon nitride film 121 at the time of a writing operation. Thus, there arises a problem that writing errors occur in a writing operation, thereby decreasing in reliability of the device.
A semiconductor device for solving the problems the problem disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2003-258128 (a document D2).
A third embodiment (hereafter of document “D2-1”) of the semiconductor device of the document D2 does not include an ONO film such as the ONO film of the document D1. The ONO film of the document D1 covers the upper surface of and both side surfaces of the control gate. The semiconductor device of the document D2-1 includes ONO films formed only on an upper surface of a substrate, each of the ONO films having a silicon nitride film which serves as a memory functional body. The semiconductor device of the document D2-1 does not include a floating gate. The semiconductor device of the document D2-1 has a metallic film with which the ONO films and the control gate are covered. In the semiconductor device of the document D2-1, the side surface of the ONO film directly contacts to the side surface of the control gate.
Since the semiconductor device of the document D2-1 does not include the floating gate, a voltage is directly applied to the control gate. Thus electrons of one of the first and second main electrode regions to which the voltage is not applied can transfer. The voltage applied to the control gate directly influences on an electron injection into the silicon nitride film during a writing operation. Therefore, by increasing the applied voltage on the control gate, the amount of the electrons injected into the silicon nitride film can be increased.
A fourth embodiment (hereafter of document D2-2) of the semiconductor device disclosed in the document D2 will now be described with reference to FIG. 2. FIG. 2 is a cross-sectional view of the semiconductor device of the document D2-2. The semiconductor device of the document D2-2 includes a substrate 211 in which a channel region 213 and first and second main electrode regions 214 sandwiching the channel region 213 are embedded. The first and second main electrode regions 214 separated from each other correspond to a source and drain. A floating gate central region 216 is formed on an upper surface of the channel region 213 via a gate oxide film 215. ONO films 217 having a thickness thinner than that of the floating gate central region 216 are formed on both side surfaces of the floating gate central region 216 and partially on the upper surface of the channel region 213. Each of the ONO films 217, in similar with the ONO films of the document D1, is configured by a lower silicon oxide film 219 serving as a memory functional body, a silicon nitride film 221, and an upper silicon oxide film 223. A floating gate side part 225 is formed so as to cover an upper surface of the ONO films 217 and the floating gate central region 216. Hereinafter, the floating gate central region 216 and the floating gate side part 225 are referenced to as a floating gate 227. The floating gate 227 of FIG. 2 corresponds to the floating gate 123 of the semiconductor device of the document D1. In the semiconductor device of the D2-2, a control gate 231 is formed so as to cover a layered body including the floating gate 227 and the ONO film 217 and additionally cover an upper surface of the substrate 211 via a silicon oxide film 229.
In the semiconductor device of the document D2-2, the upper surface of and both side surfaces of the floating gate 227 face to the control gate 231 via the silicon oxide film 229 serving as an insulation film. Thus, one surface of the floating gate 227 faces to one surface the control gate 231 via the silicon oxide film 229. A surface area of the floating gate 227 facing to the control gate 231 can be largely increased in comparison with the semiconductor device of the document D1.
In the semiconductor device of the document D2-2, only the silicon oxide film 229 serving as an insulation film is formed between the floating gate 227 and the control gate 231. The silicon oxide film 229 serving as an insulation film formed between the floating gate 227 and the control gate 231 can be decreased in its thickness in comparison with the semiconductor device of the document D1 having the ONO film configured by three films.
In the semiconductor device of the document D2-2, an electrical potential at the floating gate 227 can be easily increased in comparison with the semiconductor device of the document D1. Electrons can be easily injected into the silicon nitride film 221 during a writing operation. Thus, the semiconductor device of the document D2-2 helps solves the problem that writing errors occur in a writing operation, thereby decreasing in reliability of the device.
However, in the semiconductor device of the document D2-1 which does not include a floating gate, there is another problem. Electrons are injected into the silicon nitride film not by utilizing an induced voltage on a floating gate but applying a voltage directly to the control gate. Therefore, there is a possibility that information is written into a cell which is not intended to write due to an excess applied voltage.
The semiconductor device of the document D2-1 dose not include a floating gate, thus an electric field of the control gate is directly impressed into the silicon nitride film without intermediation of the floating gate at the time of a reading operation. The electric field of the control gate causes loss of electrons stored in the silicon nitride film of a memory functional body. Therefore, in the semiconductor device of the document D2-1, an electric field of the control gate is directly impressed into the silicon nitride film, thus causing loss of the stored electrons in the case of, for example, repeated reading operations.
The semiconductor device of the document D2-2 includes the floating gate and the ONO film entirely covering the upper surface of the channel region. The control gate is formed above the floating gate and the ONO film via the insulation film. The insulation film, the floating gate, and the ONO film are located between the channel region of the substrate and the control gate, so that the channel region does not face to the control gate at all. Therefore, it is difficult to apply a bias voltage to the channel region by applying a voltage to the control gate, thus decreasing driving ability of the semiconductor device.